1. Field of the Invention
The present invention is directed toward a M-bit folding/interpolating analog-to-digital converter circuit.
2. Related Art
In a conventional analog-to-digital converter, an analog signal is converted to a number of bits, typically between 4 bits and 10 bits. The exact number of bits in the digital word is determined by a number of factors, such as the accuracy and precision required, the cost of components, the required processing speed, available chip real-estate, and the like.
Various types of systems have been provided in the prior art for converting an input analog voltage to digital signals (currents or voltages) representative of such input analog voltage. One type of system, very often used in the prior art to provide such conversion, is known as a flash converter. In a flash converter, an analog input signal (representing the analog value to be converted digitally) is introduced to a first input of a differential amplifier in each of a plurality of repetitive cells. An individual one of a plurality of progressive fractions in a reference voltage is introduced to a second input of a respective differential amplifier.
The differential amplifier in each cell may have first and second branches each including a transistor such as MOSFET transistor. The gates of the transistors in the first and second branches respectively receive the first and second inputs. The sources of the two transistors in each differential amplifier have a common connection to a source of a substantially constant current. Load bearing currents flow through the transistors in the branches in each differential amplifier in accordance with the relative values of the voltages on the gates of the transistors, the sum of these currents being the substantially constant current.
Thus, a first output, such as a binary xe2x80x9c1xe2x80x9d, is produced in a comparator when the input voltage exceeds the particular fraction of the reference voltage introduced to the differential amplifier. Similarly, a second output, such as a binary xe2x80x9c0xe2x80x9d, is produced in the comparator when the input voltage is less than the particular fraction of the reference voltage introduced to the differential amplifier.
The demand for low-power devices and the ever increasing operation frequencies in ADC calls for ADC designs with a reduced number of power consuming comparators. In a flash ADC a common technique is used to convert an analog input signal into an eight bit (8-b) digital output code. This structure normally requires a number of 255 comparators together with a set of 255 (28xe2x88x921) reference voltages to define all the quantization levels of the ADC. If the input signal VIN exceeds the reference voltage of a comparator, the output of that comparator will be high. At the output of the comparator block, a linear code is present. The comparator block is the one who identifies the transition from high outputs to low outputs or vice-versa and establishes its dependency with the value of the input signal VIN. A binary encoder, also integrating part of the ADCs structure, converts the 255-bit code into eight binary signals. Power consumption and chip area required for the implementation of a flash AD converter are practical limits at higher sampling rates.
Alternatively, in bipolar technology the folding and interpolation technique has proven to be successful for high sample rates. Several references investigate the possibilities of usage of this technique in CMOS. The major advantage of folding and interpolation lies in the field of high sample rate in combination with low power consumption and small chip area. The folding converter requires little power to drive the input, compared to other converters. For similar reasons the power consumption of the reference ladder of the folding converter can be kept low. Previously implemented 8 bit CMOS designs achieve 85Msample/s or even 100Msample/s. But these designs have corresponding power dissipations of more than 1 Watt (W), which is to much for the embedded applications.
Several attempts have been made to design high-speed folding/interpolating ADC that can be successfully used in embedded implementations of the VLSI integrated circuits. Given the fact that design and implementation requirements of highly integrated architectures are very strict, many of the known structures for this type of ADC can no longer be used. Especially, the implementation of the converter block raises several problems related with the power consumption, signal mis-matches and large chip space requirements.
Therefore, what is needed is a design that can achieve high-speed folding, a new circuitry and a new method that permit to achieve high sampling rates per second without the correspondent power consumption.
The present invention is directed to an folding/interpolating analog-to-digital converter (ADC) that achieves low power consumption. The folding block of the present invention requires a smaller chip area and allows higher sampling rates. The present invention achieves these benefits by using an N step folding structure, as part of configuration of M-bit folding/interpolation analog-to-digital converter circuit.
Moreover, the present invention is adapted to a cascaded structure comprising a plurality of individual N step folding structures to perform the folding, as part of the ADC""s converter.
The present invention introduces an M-bit folding/interpolating analog-to-digital converter (ADC) circuit. The ADC comprises a reference voltage generator that outputs a plurality of first reference voltage signals based on an analog input signal. The ADC also comprises a converter having an amplifier that receives at least one signal from the plurality of first reference voltage signals and outputs a plurality of coarse bits. The M-bit folding/interpolating analog-to-digital converter (ADC) further comprises a number of N folding blocks, an interpolator that receives each of the folded signals form the folding blocks and outputs M times N number of interpolated outputs and a comparator. The comparator assigns one of a binary 1 and a binary 0 to each of the interpolated outputs, and outputs a binary 1 s towards the amplifier and a binary 0 as fine bits to an encoder, or outputs the binary 0 s to the amplifier and the binary is as fine bits to the encoder. The encoder receives the coarse bits and the fine bits and outputs M number of bits. M equals the sum of the coarse bits and the fine bits. Each folding block comprises a plurality of capacitors, an amplifier and a feedback element. Each capacitor has a first lead coupled to one of the plurality of first reference voltage signals. The differential amplifier has a first differential input coupled to a second lead of each of plurality of capacitors, a second differential input coupled to a second reference voltage. First and second differential outputs that output a folded signal. The feedback element has a first feedback lead coupled to at least one of first and second differential outputs and a second feedback lead coupled to first differential amplifier input.
The folding blocks of the M-bit folding/interpolating analog-to-digital converter can be implemented using switched capacitors. The folding blocks can be implemented using a plurality of equal value capacitance capacitors. The feedback element used to implement the folding blocks can be a capacitor. The value of its capacitance is X times the individual capacitance of each capacitor (said capacitor having like values). According to another embodiment of the present invention the feedback element is a field effect transistor, that performs integrating and filtering functions. According to another embodiment of the present invention a supplementary capacitor is introduced, having a first lead coupled to the second lead of each of the input capacitors and a second lead coupled to the first differential input of the differential amplifier. According to another embodiment of the present invention the folding blocks of the M-bit folding/interpolating analog-to-digital converter circuit can be implemented using a cascaded folding structure. The cascaded folding structure is implemented using a plurality of primary capacitive folding structures that output a primary folded signal. The signal constitutes input signal for a secondary folding structure constituted by a plurality secondary capacitive folding circuits that output a multiple folded signal.
In one embodiment of the invention, the output of each cell in an ADC converter is dependent upon the relative values of an analog input voltage and on each individual progressive fractions of a reference voltage signal introduced in a differential amplifier. To minimize output errors from cell mismatches, a first and second set of averaging impedances, preferably resistors, are respectively connected between the output terminals in the first branches and the output terminals in the second branches in successive pairs of cells. The impedances have relatively low values, particularly compared to the impedances of the current sources connected to the branch output terminals.
First and second resistive strips on the chip can be tapped in progressive positions to respectively define the impedances in the first and second sets. One end of each strip can be connected to the opposite end of the other strip to define a closed impedance loop for minimizing averaging errors at the strip ends. Different fractions of the reference voltage are generated based on an analog input signal associated with each individual impedance in the first and second sets. Such reference voltage fractions associated with each individual impedance have a particular repetitive relationship. In this way, the number of output terminals and cell mismatches are reduced. The different outputs at each individual impedance are determined for the progressive fractions of the reference voltage at such impedance. Successive voltage fractions for each impedance have opposite polarities to provide a folding relationship. Such outputs can be cascaded to further reduce cell mismatches and the number of output terminals.
The foregoing and other features and advantages of the present invention will be apparent from the following more particular description of the preferred embodiments of the invention, as illustrated in the accompanying drawings.